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Author SHA1 Message Date
Greg Shuflin 3599e3dbf1 Add Assembly for the SNES resource 2022-01-30 12:03:12 -08:00
Greg Shuflin b35032f28d Simple ROM with single-color screen 2022-01-30 11:46:51 -08:00
15 changed files with 364 additions and 795 deletions
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1
.gitignore vendored
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@ -1,4 +1,3 @@
*.swp
*.smc
*.obj
out/

5
README.md
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@ -4,7 +4,12 @@ This repo is a playground for messing around with SNES assembly.
It uses the [wla-dx](https://github.com/vhelin/wla-dx) assembler toolchain.
## Roms
* `simple-rom` - this is more or less following bazz's tutorial here: https://wiki.superfamicom.org/writing-your-first-snes-program
# Resources
* https://wiki.superfamicom.org/
* https://ersanio.gitbook.io/assembly-for-the-snes/

263
common/InitSNES.asm Normal file
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;------------------------------------------------------------------------
;- Written by: Neviksti
;- If you use my code, please share your creations with me
;- as I am always curious :)
;------------------------------------------------------------------------
;----------------------------------------------------------------------------
; InitSNES -- my "standard" initialization of SNES memory and registers
;----------------------------------------------------------------------------
.MACRO InitSNES
sei ;disable interrupts
clc ;switch to native mode
xce
REP #$38 ; mem/A = 16 bit, X/Y = 16 bit
;decimal mode off
LDX #$1FFF ;Setup the stack
TXS ;Transfer Index X to Stack Pointer Register
;do the rest of the initialization in a routine
JSL $008000
SEP #$20 ; mem/A = 8 bit
.ENDM
;----------------------------------------------------------------------------
.BANK 0 SLOT 0
.ORG 0
.SECTION "InitializeSNESCode" FORCE
InitializeSNES:
PHK ;set Data Bank = Program Bank
PLB
LDA #$0000 ;set Direct Page = $0000
TCD ;Transfer Accumulator to Direct Register
LDX $1FFD ;we clear all the mem at one point ...
STX $4372 ;so save the return address in a place that won't get overwritten
LDX $1FFF
STX $4374
SEP #$20 ; mem/A = 8 bit
REP #$10
LDA #$8F
STA $2100 ;turn screen off for now, set brightness to normal
LDX #$2101
_Loop00: ;regs $2101-$210C
STZ $00,X ;set Sprite,Character,Tile sizes to lowest, and set addresses to $0000
INX
CPX #$210D
BNE _Loop00
_Loop01: ;regs $210D-$2114
STZ $00,X ;Set all BG scroll values to $0000
STZ $00,X
INX
CPX #$2115
BNE _Loop01
LDA #$80 ;reg $2115
STA $2115 ; Initialize VRAM transfer mode to word-access, increment by 1
STZ $2116 ;regs $2117-$2117
STZ $2117 ;VRAM address = $0000
;reg $2118-$2119
;VRAM write register... don't need to initialize
STZ $211A ;clear Mode7 setting
LDX #$211B
_Loop02: ;regs $211B-$2120
STZ $00,X ;clear out the Mode7 matrix values
STZ $00,X
INX
CPX #$2121
BNE _Loop02
;reg $2121 - Color address, doesn't need initilaizing
;reg $2122 - Color data, is initialized later
LDX #$2123
_Loop03: ;regs $2123-$2133
STZ $00,X ;turn off windows, main screens, sub screens, color addition,
INX ;fixed color = $00, no super-impose (external synchronization),
CPX #$2134 ;no interlaced mode, normal resolution
BNE _Loop03
;regs $2134-$2136 - multiplication result, no initialization needed
;reg $2137 - software H/V latch, no initialization needed
;reg $2138 - Sprite data read, no initialization needed
;regs $2139-$213A - VRAM data read, no initialization needed
;reg $213B - Color RAM data read, no initialization needed
;regs $213C-$213D - H/V latched data read, no initialization needed
STZ $213E ;reg $213E - might not be necesary, but selects PPU master/slave mode
;reg $213F - PPU status flag, no initialization needed
;reg $2140-$2143 - APU communication regs, no initialization required
;reg $2180 - read/write WRAM register, no initialization required
;reg $2181-$2183 - WRAM address, no initialization required
;reg $4016-$4017 - serial JoyPad read registers, no need to initialize
STZ $4200 ;reg $4200 - disable timers, NMI,and auto-joyread
LDA #$FF
STA $4201 ;reg $4201 - programmable I/O write port, initalize to allow reading at in-port
;regs $4202-$4203 - multiplication registers, no initialization required
;regs $4204-$4206 - division registers, no initialization required
;regs $4207-$4208 - Horizontal-IRQ timer setting, since we disabled this, it is OK to not init
;regs $4209-$420A - Vertical-IRQ timer setting, since we disabled this, it is OK to not init
STZ $420B ;reg $420B - turn off all general DMA channels
STZ $420C ;reg $420C - turn off all H-MA channels
STZ $420D ;reg $420D - ROM access time to slow (2.68Mhz)
LDA $4210 ;reg $4210 - NMI status, reading resets
;reg $4211 - IRQ status, no need to initialize
;reg $4212 - H/V blank and JoyRead status, no need to initialize
;reg $4213 - programmable I/O inport, no need to initialize
;reg $4214-$4215 - divide results, no need to initialize
;reg $4216-$4217 - multiplication or remainder results, no need to initialize
;regs $4218-$421f - JoyPad read registers, no need to initialize
;regs $4300-$437F
;no need to intialize because DMA was disabled above
;also, we're not sure what all of the registers do, so it is better to leave them at
;their reset state value
JSR ClearVRAM ;Reset VRAM
JSR ClearPalette ;Reset colors
;**** clear Sprite tables ********
STZ $2102 ;sprites initialized to be off the screen, palette 0, character 0
STZ $2103
LDX #$0080
LDA #$F0
_Loop08:
STA $2104 ;set X = 240
STA $2104 ;set Y = 240
STZ $2104 ;set character = $00
STZ $2104 ;set priority=0, no flips
DEX
BNE _Loop08
LDX #$0020
_Loop09:
STZ $2104 ;set size bit=0, x MSB = 0
DEX
BNE _Loop09
;**** clear WRAM ********
STZ $2181 ;set WRAM address to $000000
STZ $2182
STZ $2183
LDX #$8008
STX $4300 ;Set DMA mode to fixed source, BYTE to $2180
LDX #wram_fill_byte
STX $4302 ;Set source offset
LDA #:wram_fill_byte
STA $4304 ;Set source bank
LDX #$0000
STX $4305 ;Set transfer size to 64k bytes
LDA #$01
STA $420B ;Initiate transfer
LDA #$01 ;now set the next 64k bytes
STA $420B ;Initiate transfer
PHK ;make sure Data Bank = Program Bank
PLB
CLI ;enable interrupts again
LDX $4372 ;get our return address...
STX $1FFD
LDA $4374
STA $1FFF
RTL
wram_fill_byte:
.db $00
;----------------------------------------------------------------------------
; ClearVRAM -- Sets every byte of VRAM to zero
; In: None
; Out: None
; Modifies: flags
;----------------------------------------------------------------------------
ClearVRAM:
pha
phx
php
REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
SEP #$20
LDA #$80
STA $2115 ;Set VRAM port to word access
LDX #$1809
STX $4300 ;Set DMA mode to fixed source, WORD to $2118/9
LDX #$0000
STX $2116 ;Set VRAM port address to $0000
STX $0000 ;Set $00:0000 to $0000 (assumes scratchpad ram)
STX $4302 ;Set source address to $xx:0000
LDA #$00
STA $4304 ;Set source bank to $00
LDX #$FFFF
STX $4305 ;Set transfer size to 64k-1 bytes
LDA #$01
STA $420B ;Initiate transfer
STZ $2119 ;clear the last byte of the VRAM
plp
plx
pla
RTS
;----------------------------------------------------------------------------
; ClearPalette -- Reset all palette colors to zero
; In: None
; Out: None
; Modifies: flags
;----------------------------------------------------------------------------
ClearPalette:
PHX
PHP
REP #$30 ; mem/A = 8 bit, X/Y = 16 bit
SEP #$20
STZ $2121
LDX #$0100
ClearPaletteLoop:
STZ $2122
STZ $2122
DEX
BNE ClearPaletteLoop
PLP
PLX
RTS
.ENDS

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homebrew-tutorial/charset.asm
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charset:
; tile 0x00
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
; tile 0x01
.byte %11110000 ; row 0, color 0
.byte %11111111 ; row 0, color 1
.byte %10000001 ; row 1, color 0
.byte %00000000 ; row 1, color 1
.byte %10000001 ; row 2, color 0
.byte %00000000 ; row 2, color 1
.byte %10000001 ; row 3, color 0
.byte %00001000 ; row 3, color 1
.byte %10011001 ; row 4, color 0
.byte %00001000 ; row 4, color 1
.byte %10000001 ; row 5, color 0
.byte %00000000 ; row 5, color 1
.byte %10000001 ; row 6, color 0
.byte %00000000 ; row 6, color 1
.byte %11111111 ; row 7, color 0
.byte %00000000 ; row 7, color 1
; tile 0x02
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
; This is tile 0x02 in 2bpp mode (what the background uses), but tile
; 0x01 in 4bpp mode (what the sprites use). It's very strange to mix
; these, but my assumption is that by this point you've already got
; your own graphics pipeline of some sort and probably aren't using
; 2bpp graphics at all any more, so I'm sure you can figure out what'll
; work best for you on your own :)
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
; normally you would put 14 other 8x8 tiles here, but we don't have
; any, so just fill it with zeros.
.repeat 14 * 32
.byte 0
.endrepeat
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11100000
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %00000111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %11111111
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
.byte %00000000
charset_end:

30
homebrew-tutorial/header.asm
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.segment "HEADER"
.byte "GNOSTIKKA " ; ROM name, must be 21 chars
.byte $30 ; Map Mode: 3.58MHz LoROM
.byte $00 ; Cartridge Type: ROM only
.byte $08 ; ROM Size
.byte $00 ; RAM size
.byte $01 ; Destination Code: USA
.byte $33 ; Fixed value
.byte $00 ; Mask ROM Version
.word $0000 ; Complement Check
.word $0000 ; Check Sum
; native mode vectors
.word 0, 0
.addr _rti ; COP
.addr _rti ; BRK
.addr _rti ; ABORT
.addr nmi ; NMI
.addr start ; RST
.addr _rti ; IRQ
; emulation mode vectors - largely unused, since we run in native mode
.word 0, 0
.addr 0
.addr 0
.addr 0
.addr 0
.addr start ; RST
.addr 0

49
homebrew-tutorial/init.asm
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; A very simple SNES init routine
; For serious use, you probably want to do more than this
; This is simple and understandable, though
; Will leave you in A8 XY16 mode
; Disable interrupts and enable native (i.e. not 6502-emulating) mode
sei
clc
xce
cld
setAXY16
; ZeroCPU registers NMITIMEN through MEMSEL
stz $4200
stz $4202
stz $4204
stz $4206
stz $4208
stz $420A
stz $420C
lda #$0080
sta INIDISP ; Turn off screen ("forced blank")
; Zero some registers used for rendering
stz OAMADDL
stz BGMODE
stz BG1SC
stz BG3SC
stz BG12NBA
stz VMADDL
stz W12SEL
stz WH0
stz WH2
stz WBGLOG
stz TM
stz TMW
; Disable color math / etc
ldx #$0030
stx CGWSEL
ldy #$00E0
sty COLDATA
setA8
; Zero window masks
stz WOBJSEL

17
homebrew-tutorial/keys.inc
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; Joypad bitmaps
JOYH_B = %10000000
JOYH_Y = %01000000
JOYH_SEL = %00100000
JOYH_START = %00010000
JOYH_UP = %00001000
JOYH_DOWN = %00000100
JOYH_LEFT = %00000010
JOYH_RIGHT = %00000001
JOYL_A = %10000000
JOYL_X = %01000000
JOYL_L = %00100000
JOYL_R = %00010000

33
homebrew-tutorial/lorom.cfg
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MEMORY {
ZEROPAGE: start = $000000, size = $0100;
STACK: start = $000100, size = $0100;
BSS: start = $000200, size = $1E00;
BSS7E: start = $7E2000, size = $E000;
BSS7F: start = $7F0000, size =$10000;
ROM0: start = $808000, size = $8000, fill = yes;
ROM1: start = $818000, size = $8000, fill = yes;
ROM2: start = $828000, size = $8000, fill = yes;
ROM3: start = $838000, size = $8000, fill = yes;
ROM4: start = $848000, size = $8000, fill = yes;
ROM5: start = $858000, size = $8000, fill = yes;
ROM6: start = $868000, size = $8000, fill = yes;
ROM7: start = $878000, size = $8000, fill = yes;
}
SEGMENTS {
CODE: load = ROM0, align = $100;
HEADER: load = ROM0, start = $80FFC0;
CODE1: load = ROM1, align = $100, optional=yes;
CODE2: load = ROM2, align = $100, optional=yes;
CODE3: load = ROM3, align = $100, optional=yes;
CODE4: load = ROM4, align = $100, optional=yes;
CODE5: load = ROM5, align = $100, optional=yes;
CODE6: load = ROM6, align = $100, optional=yes;
CODE7: load = ROM7, align = $100, optional=yes;
ZEROPAGE: load = ZEROPAGE, type = zp, define=yes;
BSS: load = BSS, type = bss, align = $100, optional=yes;
BSS7E: load = BSS7E, type = bss, align = $100, optional=yes;
BSS7F: load = BSS7F, type = bss, align = $100, optional=yes;
}

23
homebrew-tutorial/macros.inc
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.macro setA8
sep #$20
.endmacro
.macro setA16
rep #$20
.endmacro
.macro setAXY8
sep #$30
.endmacro
.macro setAXY16
rep #$30
.endmacro
.macro setXY8
sep #$10
.endmacro
.macro setXY16
rep #$10
.endmacro

216
homebrew-tutorial/main.asm
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.p816
.smart
.include "macros.inc"
.include "registers.inc"
.include "keys.inc"
.include "header.asm"
.segment "ZEROPAGE"
nmi_count: .res 2
.segment "BSS"
oam_lo_buffer: .res 512
oam_hi_buffer: .res 32
oam_buffer_end:
.segment "CODE"
VRAM_CHARS = $0000
VRAM_BG1 = $1000
start:
.include "init.asm"
; Set up the color palette
stz CGADD
; Color 0 - black
lda #$00
sta CGDATA
lda #$00
sta CGDATA
; Color 1 - red
lda #$1f
sta CGDATA
lda #$00
sta CGDATA
; Color 2 - green
lda #$e0
sta CGDATA
lda #$03
sta CGDATA
; Color 3 - blue
lda #$00
sta CGDATA
lda #$7c
sta CGDATA
; Set up sprite palette
lda #128 ;sprite palettes begin at cgdata index 128
sta CGADD
stz CGDATA
stz CGDATA
lda #$1f
sta CGDATA
stz CGDATA
; Graphics mode 0, 8x8 tiles
stz BGMODE
; Set BG1 and tile map and character data
lda #>VRAM_BG1
sta BG1SC
lda #VRAM_CHARS
sta BG12NBA
; Load character data into VRAM
lda #$80
sta VMAIN
ldx #VRAM_CHARS
stx VMADDL
; Set DMA source flags
lda #%00000001
sta DMAP0
; DMA destination VMDATAL register
lda #<VMDATAL
sta BBAD0
; Set starting address to charset
ldx #.loword(charset)
stx A1T0L
lda #^charset
sta A1B0
; Write to charset_end bytes
ldx #(charset_end - charset)
stx DAS0L
; actually kick off the DMA
lda #1
sta MDMAEN
; @charset_loop:
; lda charset,x
; sta VMDATAL
; inx
; lda charset,x
; sta VMDATAH
; inx
; cpx #(charset_end - charset)
; bne @charset_loop
; Manually clear screen
ldx #(VRAM_BG1)
@loop:
stx VMADDL
lda #$00
sta VMDATAL
stz VMDATAH
inx
cpx #(VRAM_BG1 + 32 * 29)
bne @loop
; write tile to position (1, 1)
TILE_X = 1
TILE_Y = 1
ldx #(VRAM_BG1 + (TILE_Y * 32) + TILE_X)
stx VMADDL
lda #$01 ; tile number
sta VMDATAL
stz VMDATAH
; Show bg1 + sprites
lda #%00010001
sta TM
lda #$0f
sta INIDISP
lda #$0
sta OBSEL
ldx #0
@zero_oam:
stz oam_lo_buffer, x
inx
cpx #(oam_buffer_end - oam_lo_buffer)
bne @zero_oam
lda #%10000001
sta NMITIMEN
mainloop:
lda nmi_count
nmi_check:
wai
cmp nmi_count
beq nmi_check
; set sprite 0 X position
ldx #$42
stx oam_lo_buffer
; set sprite 0 Y position
ldx #$69
stx oam_lo_buffer + 1
; Set sprite 0 to priority 3 and tile 0x01
ldx #((%00110000 << 8) | $0001)
stx oam_lo_buffer + 2
; Set sprite 0 to be large (16x16)
lda #%00000010
sta oam_hi_buffer
; Copy OAM data via DMA
stz OAMADDL
lda #$0
sta DMAP1
lda #<OAMDATA
sta BBAD1
ldx #.loword(oam_lo_buffer)
stx A1B1
ldx #(oam_buffer_end - oam_lo_buffer)
stx DAS1L
lda #%00000010
sta MDMAEN
lda JOY1L
bit #JOYL_L
beq down_not_pressed
; write tile 2 to position (4, 8)
TILE_X2= 4
TILE_Y2= 8
ldx #(VRAM_BG1 + (TILE_Y2* 32) + TILE_X2)
stx VMADDL
lda #$02
sta VMDATAL
stz VMDATAH
down_not_pressed:
bra mainloop
busywait:
bra busywait
nmi:
bit RDNMI
inc nmi_count
_rti:
rti
.include "charset.asm"

216
homebrew-tutorial/registers.inc
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; SNES Register Aliases
; Address Bus B Registers
INIDISP = $2100 ; Screen Display Register single write any time
OBSEL = $2101 ; Object Size and Character Size Register single write f-blank, v-blank
OAMADDL = $2102 ; OAM Address Registers (Low) single write f-blank, v-blank
OAMADDH = $2103 ; OAM Address Registers (High) single write f-blank, v-blank
OAMDATA = $2104 ; OAM Data Write Register single write f-blank, v-blank
BGMODE = $2105 ; BG Mode and Character Size Register single write f-blank, v-blank, h-blank
MOSAIC = $2106 ; Mosaic Register single write f-blank, v-blank, h-blank
BG1SC = $2107 ; BG Tilemap Address Registers (BG1) single write f-blank, v-blank
BG2SC = $2108 ; BG Tilemap Address Registers (BG2) single write f-blank, v-blank
BG3SC = $2109 ; BG Tilemap Address Registers (BG3) single write f-blank, v-blank
BG4SC = $210A ; BG Tilemap Address Registers (BG4) single write f-blank, v-blank
BG12NBA = $210B ; BG Character Address Registers (BG1&2) single write f-blank, v-blank
BG34NBA = $210C ; BG Character Address Registers (BG3&4) single write f-blank, v-blank
BG1HOFS = $210D ; BG Scroll Registers (BG1) dual write f-blank, v-blank, h-blank
BG1VOFS = $210E ; BG Scroll Registers (BG1) dual write f-blank, v-blank, h-blank
BG2HOFS = $210F ; BG Scroll Registers (BG2) dual write f-blank, v-blank, h-blank
BG2VOFS = $2110 ; BG Scroll Registers (BG2) dual write f-blank, v-blank, h-blank
BG3HOFS = $2111 ; BG Scroll Registers (BG3) dual write f-blank, v-blank, h-blank
BG3VOFS = $2112 ; BG Scroll Registers (BG3) dual write f-blank, v-blank, h-blank
BG4HOFS = $2113 ; BG Scroll Registers (BG4) dual write f-blank, v-blank, h-blank
BG4VOFS = $2114 ; BG Scroll Registers (BG4) dual write f-blank, v-blank, h-blank
VMAIN = $2115 ; Video Port Control Register single write f-blank, v-blank
VMADDL = $2116 ; VRAM Address Registers (Low) single write f-blank, v-blank
VMADDH = $2117 ; VRAM Address Registers (High) single write f-blank, v-blank
VMDATAL = $2118 ; VRAM Data Write Registers (Low) single write f-blank, v-blank
VMDATAH = $2119 ; VRAM Data Write Registers (High) single write f-blank, v-blank
M7SEL = $211A ; Mode 7 Settings Register single write f-blank, v-blank
M7A = $211B ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
M7B = $211C ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
M7C = $211D ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
M7D = $211E ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
M7X = $211F ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
M7Y = $2120 ; Mode 7 Matrix Registers dual write f-blank, v-blank, h-blank
CGADD = $2121 ; CGRAM Address Register single write f-blank, v-blank, h-blank
CGDATA = $2122 ; CGRAM Data Write Register dual write f-blank, v-blank, h-blank
W12SEL = $2123 ; Window Mask Settings Registers single write f-blank, v-blank, h-blank
W34SEL = $2124 ; Window Mask Settings Registers single write f-blank, v-blank, h-blank
WOBJSEL = $2125 ; Window Mask Settings Registers single write f-blank, v-blank, h-blank
WH0 = $2126 ; Window Position Registers (WH0) single write f-blank, v-blank, h-blank
WH1 = $2127 ; Window Position Registers (WH1) single write f-blank, v-blank, h-blank
WH2 = $2128 ; Window Position Registers (WH2) single write f-blank, v-blank, h-blank
WH3 = $2129 ; Window Position Registers (WH3) single write f-blank, v-blank, h-blank
WBGLOG = $212A ; Window Mask Logic registers (BG) single write f-blank, v-blank, h-blank
WOBJLOG = $212B ; Window Mask Logic registers (OBJ) single write f-blank, v-blank, h-blank
TM = $212C ; Screen Destination Registers single write f-blank, v-blank, h-blank
TS = $212D ; Screen Destination Registers single write f-blank, v-blank, h-blank
TMW = $212E ; Window Mask Destination Registers single write f-blank, v-blank, h-blank
TSW = $212F ; Window Mask Destination Registers single write f-blank, v-blank, h-blank
CGWSEL = $2130 ; Color Math Registers single write f-blank, v-blank, h-blank
CGADSUB = $2131 ; Color Math Registers single write f-blank, v-blank, h-blank
COLDATA = $2132 ; Color Math Registers single write f-blank, v-blank, h-blank
SETINI = $2133 ; Screen Mode Select Register single write f-blank, v-blank, h-blank
MPYL = $2134 ; Multiplication Result Registers single read f-blank, v-blank, h-blank
MPYM = $2135 ; Multiplication Result Registers single read f-blank, v-blank, h-blank
MPYH = $2136 ; Multiplication Result Registers single read f-blank, v-blank, h-blank
SLHV = $2137 ; Software Latch Register single any time
OAMDATAREAD = $2138 ; OAM Data Read Register dual read f-blank, v-blank
VMDATALREAD = $2139 ; VRAM Data Read Register (Low) single read f-blank, v-blank
VMDATAHREAD = $213A ; VRAM Data Read Register (High) single read f-blank, v-blank
CGDATAREAD = $213B ; CGRAM Data Read Register dual read f-blank, v-blank
OPHCT = $213C ; Scanline Location Registers (Horizontal) dual read any time
OPVCT = $213D ; Scanline Location Registers (Vertical) dual read any time
STAT77 = $213E ; PPU Status Register single read any time
STAT78 = $213F ; PPU Status Register single read any time
APUIO0 = $2140 ; APU IO Registers single both any time
APUIO1 = $2141 ; APU IO Registers single both any time
APUIO2 = $2142 ; APU IO Registers single both any time
APUIO3 = $2143 ; APU IO Registers single both any time
WMDATA = $2180 ; WRAM Data Register single both any time
WMADDL = $2181 ; WRAM Address Registers single write any time
WMADDM = $2182 ; WRAM Address Registers single write any time
WMADDH = $2183 ; WRAM Address Registers single write any time
; Old Style Joypad Registers
JOYSER0 = $4016 ; Old Style Joypad Registers single (write) read/write any time that is not auto-joypad
JOYSER1 = $4017 ; Old Style Joypad Registers many (read) read any time that is not auto-joypad
; Internal CPU Registers
NMITIMEN = $4200 ; Interrupt Enable Register single write any time
WRIO = $4201 ; IO Port Write Register single write any time
WRMPYA = $4202 ; Multiplicand Registers single write any time
WRMPYB = $4203 ; Multiplicand Registers single write any time
WRDIVL = $4204 ; Divisor & Dividend Registers single write any time
WRDIVH = $4205 ; Divisor & Dividend Registers single write any time
WRDIVB = $4206 ; Divisor & Dividend Registers single write any time
HTIMEL = $4207 ; IRQ Timer Registers (Horizontal - Low) single write any time
HTIMEH = $4208 ; IRQ Timer Registers (Horizontal - High) single write any time
VTIMEL = $4209 ; IRQ Timer Registers (Vertical - Low) single write any time
VTIMEH = $420A ; IRQ Timer Registers (Vertical - High) single write any time
MDMAEN = $420B ; DMA Enable Register single write any time
HDMAEN = $420C ; HDMA Enable Register single write any time
MEMSEL = $420D ; ROM Speed Register single write any time
RDNMI = $4210 ; Interrupt Flag Registers single read any time
TIMEUP = $4211 ; Interrupt Flag Registers single read any time
HVBJOY = $4212 ; PPU Status Register single read any time
RDIO = $4213 ; IO Port Read Register single read any time
RDDIVL = $4214 ; Multiplication Or Divide Result Registers (Low) single read any time
RDDIVH = $4215 ; Multiplication Or Divide Result Registers (High) single read any time
RDMPYL = $4216 ; Multiplication Or Divide Result Registers (Low) single read any time
RDMPYH = $4217 ; Multiplication Or Divide Result Registers (High) single read any time
JOY1L = $4218 ; Controller Port Data Registers (Pad 1 - Low) single read any time that is not auto-joypad
JOY1H = $4219 ; Controller Port Data Registers (Pad 1 - High) single read any time that is not auto-joypad
JOY2L = $421A ; Controller Port Data Registers (Pad 2 - Low) single read any time that is not auto-joypad
JOY2H = $421B ; Controller Port Data Registers (Pad 2 - High) single read any time that is not auto-joypad
JOY3L = $421C ; Controller Port Data Registers (Pad 3 - Low) single read any time that is not auto-joypad
JOY3H = $421D ; Controller Port Data Registers (Pad 3 - High) single read any time that is not auto-joypad
JOY4L = $421E ; Controller Port Data Registers (Pad 4 - Low) single read any time that is not auto-joypad
JOY4H = $421F ; Controller Port Data Registers (Pad 4 - High) single read any time that is not auto-joypad
; DMA/HDMA Registers
DMAP0 = $4300 ; (H)DMA Control Register
BBAD0 = $4301 ; (H)DMA Destination Register
A1T0L = $4302 ; (H)DMA Source Address Registers
A1T0H = $4303 ; (H)DMA Source Address Registers
A1B0 = $4304 ; (H)DMA Source Address Registers
DAS0L = $4305 ; (H)DMA Size Registers (Low)
DAS0H = $4306 ; (H)DMA Size Registers (High)
DASB0 = $4307 ; HDMA Indirect Address Registers
A2A0L = $4308 ; HDMA Mid Frame Table Address Registers (Low)
A2A0H = $4309 ; HDMA Mid Frame Table Address Registers (High)
NTLR0 = $430A ; HDMA Line Counter Register
DMAP1 = $4310 ; (H)DMA Control Register
BBAD1 = $4311 ; (H)DMA Destination Register
A1T1L = $4312 ; (H)DMA Source Address Registers
A1T1H = $4313 ; (H)DMA Source Address Registers
A1B1 = $4314 ; (H)DMA Source Address Registers
DAS1L = $4315 ; (H)DMA Size Registers (Low)
DAS1H = $4316 ; (H)DMA Size Registers (High)
DASB1 = $4317 ; HDMA Indirect Address Registers
A2A1L = $4318 ; HDMA Mid Frame Table Address Registers (Low)
A2A1H = $4319 ; HDMA Mid Frame Table Address Registers (High)
NTLR1 = $431A ; HDMA Line Counter Register
DMAP2 = $4320 ; (H)DMA Control Register
BBAD2 = $4321 ; (H)DMA Destination Register
A1T2L = $4322 ; (H)DMA Source Address Registers
A1T2H = $4323 ; (H)DMA Source Address Registers
A1B2 = $4324 ; (H)DMA Source Address Registers
DAS2L = $4325 ; (H)DMA Size Registers (Low)
DAS2H = $4326 ; (H)DMA Size Registers (High)
DASB2 = $4327 ; HDMA Indirect Address Registers
A2A2L = $4328 ; HDMA Mid Frame Table Address Registers (Low)
A2A2H = $4329 ; HDMA Mid Frame Table Address Registers (High)
NTLR2 = $432A ; HDMA Line Counter Register
DMAP3 = $4330 ; (H)DMA Control Register
BBAD3 = $4331 ; (H)DMA Destination Register
A1T3L = $4332 ; (H)DMA Source Address Registers
A1T3H = $4333 ; (H)DMA Source Address Registers
A1B3 = $4334 ; (H)DMA Source Address Registers
DAS3L = $4335 ; (H)DMA Size Registers (Low)
DAS3H = $4336 ; (H)DMA Size Registers (High)
DASB3 = $4337 ; HDMA Indirect Address Registers
A2A3L = $4338 ; HDMA Mid Frame Table Address Registers (Low)
A2A3H = $4339 ; HDMA Mid Frame Table Address Registers (High)
NTLR3 = $433A ; HDMA Line Counter Register
DMAP4 = $4340 ; (H)DMA Control Register
BBAD4 = $4341 ; (H)DMA Destination Register
A1T4L = $4342 ; (H)DMA Source Address Registers
A1T4H = $4343 ; (H)DMA Source Address Registers
A1B4 = $4344 ; (H)DMA Source Address Registers
DAS4L = $4345 ; (H)DMA Size Registers (Low)
DAS4H = $4346 ; (H)DMA Size Registers (High)
DASB4 = $4347 ; HDMA Indirect Address Registers
A2A4L = $4348 ; HDMA Mid Frame Table Address Registers (Low)
A2A4H = $4349 ; HDMA Mid Frame Table Address Registers (High)
NTLR4 = $434A ; HDMA Line Counter Register
DMAP5 = $4350 ; (H)DMA Control Register
BBAD5 = $4351 ; (H)DMA Destination Register
A1T5L = $4352 ; (H)DMA Source Address Registers
A1T5H = $4353 ; (H)DMA Source Address Registers
A1B5 = $4354 ; (H)DMA Source Address Registers
DAS5L = $4355 ; (H)DMA Size Registers (Low)
DAS5H = $4356 ; (H)DMA Size Registers (High)
DASB5 = $4357 ; HDMA Indirect Address Registers
A2A5L = $4358 ; HDMA Mid Frame Table Address Registers (Low)
A2A5H = $4359 ; HDMA Mid Frame Table Address Registers (High)
NTLR5 = $435A ; HDMA Line Counter Register
DMAP6 = $4360 ; (H)DMA Control Register
BBAD6 = $4361 ; (H)DMA Destination Register
A1T6L = $4362 ; (H)DMA Source Address Registers
A1T6H = $4363 ; (H)DMA Source Address Registers
A1B6 = $4364 ; (H)DMA Source Address Registers
DAS6L = $4365 ; (H)DMA Size Registers (Low)
DAS6H = $4366 ; (H)DMA Size Registers (High)
DASB6 = $4367 ; HDMA Indirect Address Registers
A2A6L = $4368 ; HDMA Mid Frame Table Address Registers (Low)
A2A6H = $4369 ; HDMA Mid Frame Table Address Registers (High)
NTLR6 = $436A ; HDMA Line Counter Register
DMAP7 = $4370 ; (H)DMA Control Register
BBAD7 = $4371 ; (H)DMA Destination Register
A1T7L = $4372 ; (H)DMA Source Address Registers
A1T7H = $4373 ; (H)DMA Source Address Registers
A1B7 = $4374 ; (H)DMA Source Address Registers
DAS7L = $4375 ; (H)DMA Size Registers (Low)
DAS7H = $4376 ; (H)DMA Size Registers (High)
DASB7 = $4377 ; HDMA Indirect Address Registers
A2A7L = $4378 ; HDMA Mid Frame Table Address Registers (Low)
A2A7H = $4379 ; HDMA Mid Frame Table Address Registers (High)
NTLR7 = $437A ; HDMA Line Counter Register

14
justfile
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default:
just --list
# Run homebrew ROM using mesen-s
run-homebrew: homebrew-tutorial
mesen-s ./out/main.sfc
# Build homebrew ROM in ./out
homebrew-tutorial:
mkdir -p out
ca65 ./homebrew-tutorial/main.asm -o ./out/main.o -g
ld65 -C ./homebrew-tutorial/lorom.cfg -o ./out/main.sfc ./out/main.o
simple_rom:
#!/usr/bin/env bash
cd simple-rom
wla-65816 -o simple_rom.obj simple_rom.asm
wlalink simple_rom.link simple_rom.smc
greenspace_smc:
just legacy/greenspace/greenspace_smc

61
simple-rom/header.inc Normal file
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;------------------------------ Header File ---------------------------------
; This is basically a combo of MarctheMER's and Neviksti's header files
; Perhaps reading their's will also help your understanding of the header,
; but I believe this will be the simplest method of defining your header,
; as Marc's doesn't provide a full explanation, and Neviksti's can be
; a bit more difficult for beginners (using the WLA directives is easier).
;----------------------------------------------------------------------------
;==LoRom== ; We'll get to HiRom some other time.
.MEMORYMAP ; Begin describing the system architecture.
SLOTSIZE $8000 ; The slot is $8000 bytes in size.
DEFAULTSLOT 0 ; There's only 1 slot in SNES
SLOT 0 $8000 ; Define's Slot 0's starting address.
.ENDME ; End MemoryMap definition
.ROMBANKSIZE $8000 ; Every ROM bank is 32 KBytes in size
.ROMBANKS 8 ; 2 Mbits - Tell WLA we want to use 8 ROM Banks
.SNESHEADER
ID "SNES" ; 1-4 letter string, just leave it as "SNES"
NAME "Test SNES ROM desu " ; Program Title - can't be over 21 bytes,
; "123456789012345678901" ; use spaces for unused bytes of the name.
SLOWROM
LOROM
CARTRIDGETYPE $00 ; $00 = ROM only, see WLA documentation for others
ROMSIZE $08 ; $08 = 2 Mbits, see WLA doc for more..
SRAMSIZE $00 ; No SRAM see WLA doc for more..
COUNTRY $01 ; $01 = U.S. $00 = Japan, that's all I know
LICENSEECODE $00 ; Just use $00
VERSION $00 ; $00 = 1.00, $01 = 1.01, etc.
.ENDSNES
.SNESNATIVEVECTOR ; Define Native Mode interrupt vector table
COP EmptyHandler
BRK EmptyHandler
ABORT EmptyHandler
NMI EmptyHandler
IRQ EmptyHandler
.ENDNATIVEVECTOR
.SNESEMUVECTOR ; Define Emulation Mode interrupt vector table
COP EmptyHandler
ABORT EmptyHandler
NMI EmptyHandler
RESET Start
IRQBRK EmptyHandler
.ENDEMUVECTOR
.BANK 0 SLOT 0 ; Defines the ROM bank and the slot it is inserted in memory.
.ORG 0 ; .ORG 0 is really $8000, because the slot starts at $8000
.SECTION "EmptyVectors" SEMIFREE
EmptyHandler:
rti
.ENDS
.EMPTYFILL $00
;---------------------------------- END -------------------------------------

28
simple-rom/simple_rom.asm Normal file
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;== Include memorymap, header info, and SNES initialization routines
.INCLUDE "header.inc"
.INCLUDE "../common/InitSNES.asm"
;========================
; Start
;========================
.BANK 0 SLOT 0
.ORG 0
.SECTION "MainCode"
Start:
InitSNES ; invoke SNES init
stz $2121 ; set $2121 to zero, this sets palette color 0
lda #%00010011 ; binary is more visual, but if you
sta $2122 ; Colors are 2 bytes. Write first byte from A
stz $2122 ; second byte is 0
lda #$0F ; = 00001111
sta $2100 ; Turn on screen, full brightness
forever:
jmp forever
.ENDS

2
simple-rom/simple_rom.link Normal file
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[objects]
simple_rom.obj