2016-12-05 19:24:36 -08:00
|
|
|
.include "header.inc"
|
|
|
|
.include "snes_init.asm"
|
2016-12-06 02:51:01 -08:00
|
|
|
.include "my_custom.asm"
|
2016-12-05 19:24:36 -08:00
|
|
|
|
|
|
|
.BANK 0 SLOT 0
|
|
|
|
.org 0
|
|
|
|
.section "Vblank"
|
|
|
|
|
|
|
|
VBlank:
|
|
|
|
rti
|
|
|
|
|
|
|
|
.ENDS
|
|
|
|
|
|
|
|
.BANK 0 SLOT 0
|
|
|
|
.ORG 0
|
|
|
|
.section "Main"
|
|
|
|
|
2016-12-07 01:13:29 -08:00
|
|
|
.MACRO Video_Port_Control
|
|
|
|
;VRAM transfer, word-access, increment by 1
|
|
|
|
lda #%10000000
|
|
|
|
sta $2115
|
|
|
|
.ENDM
|
|
|
|
|
|
|
|
;assumes 8-bit a, 16-bit xy
|
|
|
|
.MACRO Load_Block_to_VRAM ARGS SOURCE DEST SIZE
|
|
|
|
Video_Port_Control
|
|
|
|
|
|
|
|
ldx #DEST
|
|
|
|
stx $2116 ; $2116/2117 is 2byte address for VRAM upload/download. most significant bit must be 0
|
|
|
|
|
|
|
|
lda #:SOURCE ; source bank
|
|
|
|
ldx #SOURCE ; source offset
|
|
|
|
ldy #SIZE
|
|
|
|
|
|
|
|
stx $4302 ; store data offset into DMA control register
|
|
|
|
sta $4304 ; store bank into DMA source bank
|
|
|
|
sty $4305 ; store size of block
|
|
|
|
|
|
|
|
lda #$01
|
|
|
|
sta $4300 ; set DMA mode (word, normal increment)
|
|
|
|
|
|
|
|
lda #$18
|
|
|
|
sta $4301 ; set destination register (VRAM write register) - add value to $2100 to get destination address
|
|
|
|
; i.e. this is writing to $2118, which when written writes a byte to VRAM
|
|
|
|
|
|
|
|
lda #$01
|
|
|
|
sta $420b ; and start the transfer
|
|
|
|
.ENDM
|
|
|
|
|
2016-12-05 19:24:36 -08:00
|
|
|
Start:
|
|
|
|
Snes_Init
|
|
|
|
|
2016-12-07 01:13:29 -08:00
|
|
|
Set_A_8_XY_16
|
2016-12-05 19:24:36 -08:00
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $ff, $0a
|
2016-12-05 19:24:36 -08:00
|
|
|
|
2016-12-07 01:13:29 -08:00
|
|
|
Set_Screen_Brightness %00001111
|
2016-12-05 19:24:36 -08:00
|
|
|
|
2016-12-07 01:13:29 -08:00
|
|
|
lda #%00000000 ; 8x8 for all 4 backgrounds, no priority flip, Mode: 4 colors/tile w/ 32 palettes
|
|
|
|
sta $2105 ; store to screen mode register
|
|
|
|
|
|
|
|
; size (last argument) depends on color mode
|
|
|
|
; location is beginning of VRAM
|
|
|
|
Load_Block_to_VRAM Face, $0000, (8*2*2),
|
|
|
|
|
|
|
|
; put character data at VRAM $0000, tile data at $0400
|
|
|
|
lda #$04
|
|
|
|
sta $2107 ; BG1 tile map location (upper 6 bits)
|
|
|
|
lda #$00
|
|
|
|
sta $210b ; BG1 character location ($1000 word intervals - can't go over $8000 b/c size of VRAM)
|
|
|
|
|
|
|
|
; main screen designation
|
|
|
|
lda #%00000001
|
|
|
|
sta $212c ; enable bkg 1,
|
|
|
|
|
2016-12-07 02:14:42 -08:00
|
|
|
ldx #$04f0 ; load $0400 (VRAM address of tile data)
|
2016-12-07 01:13:29 -08:00
|
|
|
stx $2116 ; and store it to VRAM address word-sized register
|
|
|
|
|
|
|
|
ldx #$0001
|
2016-12-07 02:14:42 -08:00
|
|
|
stx $2118 ;store tile map entry to the address specified in $2116 - this increments or not based on 2115
|
2016-12-05 19:24:36 -08:00
|
|
|
|
|
|
|
|
|
|
|
lda #%10000001 ; enable NMI and joypads
|
|
|
|
sta $4200
|
|
|
|
|
|
|
|
mainloop:
|
|
|
|
Spin_Loop $02
|
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
Reset_Palette_Offset
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $ff, $0a
|
2016-12-05 19:24:36 -08:00
|
|
|
|
|
|
|
Spin_Loop $02
|
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
Reset_Palette_Offset
|
|
|
|
Load_Palette_Color $ff, $a0
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $00, $00
|
|
|
|
Load_Palette_Color $ff, $0a
|
2016-12-05 19:24:36 -08:00
|
|
|
|
|
|
|
jmp mainloop
|
|
|
|
|
|
|
|
.ENDS
|
|
|
|
|
|
|
|
|
|
|
|
.BANK 1 SLOT 0
|
|
|
|
.org 0
|
|
|
|
.section "TileData"
|
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
Face:
|
2016-12-07 01:13:29 -08:00
|
|
|
|
|
|
|
.db $00, $00, $00, $00, $00, $00, $00, $00
|
|
|
|
.db $00, $00, $00, $00, $00, $00, $00, $00
|
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
.db %00000000
|
|
|
|
.db %00000000
|
|
|
|
|
|
|
|
.db %11000011
|
|
|
|
.db %11000011
|
|
|
|
|
|
|
|
.db %11000011
|
|
|
|
.db %11000011
|
|
|
|
|
|
|
|
.db %00111000
|
|
|
|
.db %00111000
|
|
|
|
|
|
|
|
.db %00111000
|
|
|
|
.db %00111000
|
|
|
|
|
|
|
|
.db %10000001
|
|
|
|
.db %10000001
|
2016-12-05 19:24:36 -08:00
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
.db %01000010
|
|
|
|
.db %01000010
|
2016-12-05 19:24:36 -08:00
|
|
|
|
2016-12-06 02:51:01 -08:00
|
|
|
.db %00111100
|
|
|
|
.db %00111100
|
2016-12-05 19:24:36 -08:00
|
|
|
|
|
|
|
.ENDS
|