76 lines
2.0 KiB
Verilog
76 lines
2.0 KiB
Verilog
module top(output N, output E, output W, output S, output G, input hwclock, output pmod_1, input pmod_2, output ftdi_tx);
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reg [31:0] counter = 32'b0;
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assign G = counter[21];
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assign N = counter[22];
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wire busy;
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serial foo (hwclock, "q", 0, 1, ftdi_tx, busy);
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always @ (posedge hwclock) begin
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counter <= counter + 1;
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end
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endmodule
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module serial(input hwclock, input [7:0] char, input reset, input send, output reg out, output busy);
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reg [12:0] counter;
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reg [7:0] char1;
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assign busy = (state == IDLE) ? 1'b1 : 1'b0;
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localparam IDLE = 4'd0, START = 4'd1;
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localparam BIT0 = 4'd2, BIT1 = 4'd3, BIT2 = 4'd4, BIT3 = 4'd5, BIT4 = 4'd6,
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BIT5 = 4'd7, BIT6 = 4'd8, BIT7 = 4'd9, STOP = 4'd10;
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localparam SPACE = 1'b0;
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localparam MARK = 1'b1;
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reg [3:0] state = IDLE;
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always @ (posedge hwclock) begin
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if (reset) begin
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state <= IDLE;
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counter <= 0;
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end else if (state == IDLE) begin
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if (send == 1) begin
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state <= START;
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counter <= 0;
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char1 <= char;
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end
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end else begin
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// 12_000_000 / 9600 = 1250
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if (counter < 1250) begin
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counter <= counter + 1;
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end else begin
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counter <= 0;
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if (state != STOP) begin
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state <= state + 1'b1;
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end else begin
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state <= IDLE;
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end
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end
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end
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end
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always @ (*) begin
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case (state)
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IDLE: out = MARK; // Stop bit is also IDLE
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START: out = SPACE;
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BIT0: out = char1[0];
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BIT1: out = char1[1];
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BIT2: out = char1[2];
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BIT3: out = char1[3];
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BIT4: out = char1[4];
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BIT5: out = char1[5];
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BIT6: out = char1[6];
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BIT7: out = char1[7];
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default: out = MARK;
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endcase
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end
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endmodule
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